A reconfigurable architecture includes chips (VPU) with configurable function and/or networking, particularly integrated chips with a multiplicity of arithmetic and/or logic and/or analog and/or storing and/or networking modules arranged one-dimensionally or multidimensionally (called PAEs in the text which follows) and/or communicative/peripheral modules (IO) which are connected to one another either directly or by one or more bus system(s). PAEs are arranged in any design, mixture and hierarchy. This arrangement will be called PAE array or PA in the further text.
The conventional type of these chips includes systolic arrays, neuron networks, multiprocessor systems, processors having a number of arithmetic logic units and/or logic cells, networking and network chips such as e.g. crossbar switches and also known chips of the conventional FPGA, DPGA, XPUTER etc. type. Particular reference is made in this context to the following patents by the same applicant: P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 044.6-53, DE 198 80 129.7, DE 198 61 088.2-53, DE 199 80 312.9, PCT/DE 00/01869, DE 100 36 627.9-33, DE 100 28 397.7, DE 101 10 530.4, DE 101 11 014.6, PCT/EP 00/10516, EP 01 102 674.7, each of which is expressly incorporated herewith by reference in its entirety.
It should also be noted that the methods can also be applied to groups of a number of chips.